The present invention relates to semiconductor integrated circuit testing and more particularly relates to burn-in testing of semiconductor integrated circuit devices.
After semiconductor devices are produced, a screening and testing operation may be performed to detect and remove defective electronic devices to ensure the overall quality of the devices. In one such screening operation, a burn-in stress test may be executed that involves both field acceleration and temperature acceleration. During burn-in stress testing, the device may be operated in a state where the voltage and temperature of the test are set much higher than the normal operating voltage and temperature of the device. A stress voltage higher than that which frequently causes initial failure during normal operation may be applied to the device for a period of time. As a result, a defective device may be removed from production. Without burn-in testing, this defective device might have not been detected until the device""s initial operation.
The burn-in testing stresses chips through elevation of temperature and voltage and induces weak devices and other structures to fail prior to being released to the field. An objective of stress testing is to identify defective devices at the earliest part of the fabrication process. However, as technology scales, there has been a need to reduce the power supply voltage of chips. Reducing the power supply voltage of chips while maintaining the same threshold voltage for transistors on the chip may degrade the performance of the chip. As such, if the power supply voltage and the threshold voltages are reduced, then leakage current on the chip increases. Leakage current is a major problem that causes a barrier to scaling technology. This problem is more pronounced at burn-in because of the elevated temperature and voltage. It is desirable to deal with burn-in technology without causing leakage current problems in order to screen scaled integrated circuits having increased speeds.